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IDT74FCT16260AT/CT/ET FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
FEATURES:
* * * * *
IDT74FCT16260AT/CT/ET
DESCRIPTION:
* * * * * *
0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tSK(o) (Output Skew) < 250ps Low input and output leakage 1A (max.) ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) VCC = 5V 10% High drive outputs (-32mA IOH, 64mA IOL) Power off disable outputs permit "live insertion" Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25C Power off disable outputs permit "live insertion" Available in SSOP and TSSOP packages
The FCT16260T Tri-Port Bus Exchangers are high-speed 12-bit latched bus multiplexers/transceivers for use in high-speed microprocessor applications. These Bus Exchangers support memory interleaving with latched outputs on the B ports and address multiplexing with latched inputs on the B ports. The Tri-Port Bus Exchanger has three 12-bit ports. Data may be transferred between the A port and either/both of the B ports. The latch enable (LE1B, LE2B, LEA1B and LEA2B) inputs control data storage. When a latch-enable input is high, the latch is transparent. When a latch-enable input is low, the data at the input is latched and remains latched until the latch enable input is returned high. Independent output enables (OE1B and OE2B) allow reading from one port while writing to the other port. The FCT16260T is ideally suited for driving high capacitance loads and low impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers.
FUNCTIONAL BLOCK DIAGRAM
29
OE1B
30
LEA1B
A-1B LATCH
12
1B1:12
2
LE1B
12 28 1 12
1B-A LATCH
12
SEL OEA A1:12
12
M1 U X0
12 12 27
LE2B
2B-A LATCH
12
55
LEA2B
56
A-2B LATCH
12
2B1:12
OE2B
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 2002 Integrated Device Technology, Inc.
JANUARY 2002
DSC-5431/2
IDT74FCT16260AT/CT/ET FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OEA LE1B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 LE2B SEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 OE2B LEA2B 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 LEA1B OE1B
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) VTERM(3) TSTG IOUT Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max -0.5 to 7 -0.5 to VCC+0.5 -65 to +150 -60 to +120 Unit V V C mA
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXX Output and I/O terminals. 3. Output and I/O terminals for FCT162XXX.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. 6 8 Unit pF pF
NOTE: 1. This parameter is measured at characterization but not tested.
SSOP/ TSSOP TOP VIEW
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IDT74FCT16260AT/CT/ET FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Signal A(1:12) 1B(1:12) 2B(1:12) LEA1B LEA2B LE1B LE2B SEL OEA OE1B OE2B I/O I/O I/O I/O I I I I I I I I Description Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus. Bidirectional Data Port 1B. Connected to the even path or even bank of memory. Bidirectional Data Port 2B. Connected to the odd path or odd bank of memory. Latch Enable Input for A-1B Latch. The Latch is open when LEA1B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LEA1B. Latch Enable Input for A-2B Latch. The Latch is open when LEA2B is HIGH. Data from the A-Port is latched on the HIGH to LOW transition of LEA2B. Latch Enable Input for the 1B-A Latch. The Latch is open when LE1B is HIGH. Data from the 1B port is latched on the HIGH to LOW transition of LE1B. Latch Enable Input for the 2B-A Latch. The Latch is open when LE2B is HIGH. Data from the 2B port is latched on the HIGH to LOW transition of LE2B. 1B or 2B Path Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables data transfer from 2B Port to A Port. Output Enable for A Port (Active LOW) Output Enable for 1B Port (Active LOW) Output Enable for 2B Port (Active LOW)
FUNCTION TABLES(1)
1B H L X X X X X 2B X X X H L X X SEL H H H L L L X Inputs LE1B H H L X X X X LE2B X X X H H L X OEA L L L L L L H Output A H L A(1) H L A(1) Z Outputs OE1B L L L L L L L H L H L OE2B L L L L L L L H H L L 1B H L H L B(1) B(1) B(1) Z Active Z Active 2B H L B(1) B(1) H L B(1) Z Z Active Active
A H L H L H L X X X X X
LEA1B H H H H L L L X X X X
Inputs LEA2B H H L L H H L X X X X
NOTES: 1. Output level before the indicated steady-state input conditions were established. 2. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance
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IDT74FCT16260AT/CT/ET FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 10%
Symbol VIH VIL IIH Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input pins)(5) Input HIGH Current (I/O pins)(5) IIL Input LOW Current (Input pins)(5) Input LOW Current (I/O pins)(5) IOZH IOZL VIK IOS VH ICCL ICCH ICCZ High Impedance Output Current (3-State Output pins)(5) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current VCC = Max. VIN = GND or VCC VCC = Min., IIN = -18mA VCC = Max., VO = GND(3) -- VCC = Max. VO = 2.7V VO = 0.5V VI = GND Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC Min. 2 -- -- -- -- -- -- -- -- -80 -- -- Typ.(2) -- -- -- -- -- -- -- -- -0.7 -140 100 5 Max. -- 0.8 1 1 1 1 1 1 -1.2 -250 -- 500 V mA mV A A Unit V V A
OUTPUT DRIVE CHARACTERISTICS
Symbol IO VOH Parameter Output Drive Current Output HIGH Voltage Test Conditions(1) VCC = Max., VO = 2.5V(3) VCC = Min. IOH = -3mA VIN = VIH or VIL IOH = -15mA IOH = -32mA(4) VCC = Min. IOL = 64mA VIN = VIH or VIL VCC = 0V, VIN or VO 4.5V Min. -50 2.5 2.4 2 -- -- Typ.(2) -- 3.5 3.5 3 0.2 -- Max. -180 -- -- -- 0.55 1 Unit mA V V A
VOL IOFF
Output LOW Voltage Input/Output Power Off Leakage(5)
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is 5A at TA = -55C.
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IDT74FCT16260AT/CT/ET FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open One Output Port Enabled LExx = VCC One Input Bit Togging One Output Bit Toggling 50% Duty Cycle VCC = Max. Outputs Open fi = 10MHz 50% Duty Cycle One Output Port Enabled LExx = VCC One Input Bit Toggling One Output Bit Toggling VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle One Output Port Enabled LExx = VCC Twelve Input Bits Toggling Twelve Output Bits Toggling VIN = VCC VIN = GND Test Conditions(1) Min. -- -- Typ.(2) 0.5 60 Max. 1.5 100 Unit mA A/ MHz
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
0.6
1.5
mA
--
0.9
2.3
VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
1.8
3.5(5)
--
4.8
12.5(5)
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V). DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
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IDT74FCT16260AT/CT/ET FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16260AT Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW tSK(o) Parameter Propagation Delay Ax to 1Bx or Ax to 2Bx Propagation Delay 1Bx to Ax or 2Bx to Ax Propagation Delay LExB to Ax Propagation Delay LEA1B to 1Bx or LEA2B to 2Bx Propagation Delay SEL to Ax Output Enable Time OEA to Ax, OE1B to 1Bx, or OE2B to 2Bx Output Disable Time OEA to Ax, OE1B to 1Bx, or OE2B to 2Bx Set-up Time HIGH or LOW Data to Latch Hold Time, Latch to Data Pulse Width, Latch HIGH (4) Output Skew(3) 1.5 1.5 1.5 1 3 -- 5.7 4.4 -- -- -- 0.5 1.5 1.5 1 1 3 -- 5.1 4 -- -- -- 0.5 1.5 1.5 1 1 3 -- 4.4 4 -- -- -- 0.5 ns ns ns ns ns ns 1.5 5.2 1.5 4.7 1.5 4 ns 1.5 4.7 1.5 4.4 1.5 4 ns 1.5 5.2 1.5 4.7 1.5 4 ns Condition(1) CL = 50pF RL = 500 1.5 5.6 1.5 5 1.5 3.6 ns Min.(2) 1.5 Max. 5.2 FCT16260CT Min.(2) 1.5 Max. 4.7 FCT16260ET Min.(2) 1.5 Max. 3.6 Unit ns
NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This parameter is guaranteed but not tested.
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IDT74FCT16260AT/CT/ET FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
Test Open Drain Disable Low Enable Low
7.0V
Switch Closed Open
V CC
All Other Tests
500 V IN Pulse Generator D.U.T. 50pF RT 500 CL V OUT
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
DATA INPUT tSU TIM ING INPUT ASYNCHRONOUS CONTROL PRES ET CLEA R ETC. SYNCHRONOUS CONTROL PRES ET CLEA R CLOCK ENABLE ETC. tREM
tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
LOW -HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE
1.5V
1.5V
tSU
tH
Pulse Width
Set-up, Hold, and Release Times
ENABLE SAM E PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE P HASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V DISABLE 3V CONTROL INPUT tPZL OUTPUT NORM ALLY LOW SW ITCH CLOSED tPZH OUTPUT NORM ALLY HIGH SW ITCH OPEN 3.5V 1.5V 0.3V tPHZ 0.3V 1.5V 0V 0V VOH tPLZ 1.5V 0V 3.5V VOL
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
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IDT74FCT16260AT/CT/ET FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX Temp. Range FCT XXX Family XXXX Device Type XX Package
PV PA
Shrink Sm all Outline Package Thin Shrink Small Outline Package
206AT 206CT 206ET
12-Bit Tri-Port Bus Exchanger
16
Double-Density, 5 Volt, Balanced Drive
74
- 40C to +85C
DATA SHEET DOCUMENT HISTORY 1/21/2002 Removed Military temp grade
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